1. Technical Field
The present invention relates in general to data processing and, in particular, to improved data processing system and cache memories for data processing systems. Still more particularly, the present invention relates to speculative processing of stores following synchronizing operations in a cache memory of a data processing system.
2. Description of the Related Art
Multiprocessor data processing system implement a variety of consistency models that govern the order in which memory access instructions are performed with respect to a shared memory. For example, in multiprocessor data processing system implementing a strongly consistent memory model, memory accesses are performed with respect to shared memory strictly in program order. Weakly consistent architectures, on the other hand, permit some reordering of memory access operations as long as data dependencies are observed and any given processor does not access an older value of a memory location (i.e., “stale” data) after accessing a newer value of the same memory location.
Because weakly consistent architectures permit the memory access operations comprising a sequence of memory access operations to be performed in a variety of different orders, programmers commonly place barrier instructions within the instruction sequence to enforce a desired ordering among the memory access operations. In particular, a barrier instruction ensures that all memory access operations indicated by the instructions preceding the barrier instruction are visible to all processors before any memory access operation initiated by an instruction subsequent to the barrier instruction is performed. In a typical implementation, the barrier instruction, when executed by a processor, generates a barrier operation communicated to all other processors in the multiprocessor data processing system via an interconnect. When each of the other processors completes all memory access instructions preceding the barrier operation, the processors transmit acknowledgements of the barrier operation to the issuing processor, which completes the barrier operation and then permits subsequent memory access operations to be performed.
Barrier instructions and the associated barrier operations significantly burden data processing system efficiency by causing pipeline stalls within the processors, utilizing bandwidth on the system interconnect, and creating inefficiencies in the handling of memory access operations by the cache memories supporting the processors.